DDRSS Validation Engineer (RTL + Silicon Debug)

Qualcomm•San Diego, CA

7d•$140,000 - $210,000

About The Position

We are seeking a highly motivated validation engineer with strong debugging and firmware development skills to support next-generation SoC platforms. This role spans pre-silicon verification, emulation, and post-silicon validation, with a focus on deep debug in RTL/Verilog environments and hands-on silicon bring-up. The ideal candidate will bridge the gap between design, DV, and system validation by developing firmware in C and ensuring robust functionality across simulation, emulation, and silicon platforms.

Requirements

6–9 years of experience in SoC validation, design verification, or post-silicon validation
Strong debug skills in Verilog/SystemVerilog simulation environments
Experience with firmware development in C for embedded systems
Hands-on experience with silicon bring-up, debug, and validation
Experience debugging across multiple platforms (simulation, emulation, silicon)
Solid understanding of Computer architecture and SoC subsystems
Solid understanding of Memory systems (DDR, cache, interconnect)
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

Drive end-to-end validation of SoC subsystems (DDR, memory controller, cache, interconnect) across RTL simulation (Verilog/SystemVerilog), Emulation platforms, and Post-silicon environments.
Perform deep debug of functional issues including root-causing failures in RTL simulations and testbenches, debugging firmware-driven flows, and analyzing silicon failures (timing, stability, performance).
Develop and maintain production quality firmware in C to manage DDRSS IP sequences through init, frequency and power management, enable bring-up and feature validation, and exercise system-level use cases.
Support debug and characterization.
Validate firmware across RTL simulation environments, Emulation systems, and Silicon platforms.
Collaborate cross-functionally with Design (RTL/architecture teams), DV teams (testbench and coverage alignment), and System and silicon validation teams.
Develop tools, debug infrastructure, and automation to improve validation efficiency, data collection and analysis, and failure triage and turnaround time.