DDR PHY AMS Engineer

Advanced Micro Devices, Inc•Boxborough, MA

2h•Hybrid

About The Position

The candidate will be a Member of the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of algorithms for calibration, equalization and development of abstracted models for link performance simulations.

Requirements

Strong experience building Memory Phys and High-speed IOs with track record of multiple successful Tape-out and productization.
Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation.
Strong/effective communication skills
Enthusiastic team-first mentality

Nice To Haves

A proven successful track record in circuit-architecture and modeling for High Speed Ios
A proven track record of leading junior engineers to deliver complex circuits
Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Ability to dig into RTL or FW code supporting the custom circuit implementation

Responsibilities

Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHY
Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, Delay Lines, DAC, OpAmp, Comparator and voltage regulators
Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation
Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
Participate and contribute to the definition of development flows that improve efficiency and quality of execution
Lead design liaison for post Silicon characterization and productization/volume production efforts