UEFI

Qualcomm•Santa Clara, CA

7d•$172,400 - $258,600

About The Position

The Sr Staff ARM Server Firmware Management Customer Engineer is a senior technical authority responsible for driving the success of ARM based, hyperscale class server platforms across hyperscalers, OEMs/ODMs, cloud providers, and strategic enterprise partners. This role combines deep platform firmware expertise, server architecture insight, and customer facing leadership to accelerate adoption, solve the industry’s most complex system level issues, and influence long term product direction across Qualcomm’s datacenter roadmap. As a Sr Staff engineer, you will operate with broad technical latitude across UEFI/BIOS, BMC/Manageability (Redfish/IPMI/PLDM/MCTP/KCS), ARM Trusted Firmware, silicon initialization, platform RAS, and system level telemetry, leading multi team debug and integration efforts, mentoring customer engineering teams, and serving as the final escalation point for mission critical deliverables.

Requirements

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Applications Engineering, Software Development experience, or related work experience.
OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Applications Engineering, Software Development experience, or related work experience.
OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Applications Engineering, Software Development experience, or related work experience.
3+ years of experience with Programming Language such as C, C++, Java, Python, etc.
3+ years of experience with debugging techniques.

Nice To Haves

Master’s in Computer Engineering / Electrical Engineering / Computer Science, or related field.
12–17+ years in firmware, bootloader, or system software development for ARM or datacenter server platforms.
Expert level understanding of: UEFI/EDK2 (PEI/DXE), secure/Measured Boot, TPM event logs, capsule updates, runtime services; host–BMC coordination and BIOS–BMC attribute sync.
Expert level understanding of: ARMv8/v9 (EL0–EL3), MMU/SMMU/IOMMU, RAS (APEI/CPER/SDEI/SError), SEA/SEI handling, error containment & recovery models.
Expert level understanding of: BMC ecosystems: OpenBMC, Redfish, IPMI, KCS host interface, PLDM (Base, FRU, BIOS Control & Configuration, Monitoring & Eventing, Firmware Update), MCTP (endpoints & transports over SMBus/I³C/PCIe VDM), SOL/vUART, SEL/SDR/FRU management.
Expert level understanding of: PCIe/CXL (enumeration, LTSSM, equalization) with AER/DPC/ACS/ARI/ECRC, and DDR bring up (PHY training, margining, ECC).
Deep debugging using JTAG/Trace32, early boot traces, silicon waveforms, CPER/AER event triage, fault injection and telemetry pipelines (Redfish/PLDM/host logs).
Proven experience leading customer facing escalations at hyperscale, conducting architecture reviews, and executing cross domain root cause investigations to closure.
Leadership across host firmware, BMC manageability, platform security, and RAS—from design to fleet scale sustainment.
Demonstrated delivery against SystemReady SR, SBSA/SBBR, ACPI/SMBIOS, and Redfish/PLDM conformance; hands on with PLDM FW Update orchestration and MCTP routing/bridging.
Expertise in fault detection, error handling, and recovery (e.g., CPER driven policies, AER/DPC reactions, memory poison flows for DDR/CXL, graceful isolation/degrade continue strategies).
Ability to influence senior stakeholders, shape long range platform strategy, and operate independently in ambiguous, high severity, customer driven environments.

Responsibilities

Act as the ultimate escalation point for boot blockers, firmware regressions, PCIe/CXL link training or RAS faults, DDR PHY training issues, secure boot and attestation failures, and host–BMC synchronization defects.
Perform deep dive forensics across crash dumps, firmware traces, silicon trace buffers, CPER records, AER/DPC events, SEL/IPMI logs, Redfish telemetry, PLDM monitoring, and cross domain error propagation.
Run cross functional war rooms with silicon, firmware, BIOS, BMC/Manageability, validation, and security stakeholders to deliver rapid containment and durable fixes.
Serve as the principal technical interface for hyperscalers and OEM/ODMs on: UEFI/BIOS and TF A bring up; BMC integration; Redfish service design; PLDM based host coordination; MCTP endpoint/transport setup; KCS/SSIF/IPMB host BMC channels; and secure firmware lifecycle.
Lead code/design reviews for UEFI drivers, TF A components, and BMC services (PLDM Base/FRU/BIOS Control & Config/Monitoring, Redfish schemas, telemetry streaming).
Deliver high value collateral: bring up guides, error handling/RAS playbooks, debug procedures, Redfish/PLDM modeling guidance, and architecture recommendations.
Lead integration across: UEFI/EDK2 (PEI/DXE), ARM Trusted Firmware (TF A, TF RMM), ACPI/SMBIOS construction.
Lead integration across: BMC firmware (OpenBMC or equivalent) including Redfish, IPMI, KCS, PLDM over MCTP, MCTP transports (SMBus/I³C/PCIe VDM), SOL/vUART/SoL, sensor & SDR frameworks, FRU data, and BIOS–BMC attribute sync.
Lead integration across: PCIe/CXL initialization (LTSSM, link equalization), AER/DPC policy, RCEC interactions; DDR PHY training & margining; runtime services (PSCI/SDEI).
Shape the end to end diagnostics and observability stack: early boot logging, host–BMC log correlation, Redfish telemetry, fault injection frameworks, JTAG/Trace32 multi domain traces, and error persistence strategies.
Mentor internal engineers; scale customer engineering capabilities globally.
Identify systemic gaps in fault detection, error handling, recoverability, and manageability protocol interoperability; drive architectural fixes and process improvements.
Contribute to ecosystem alignment on SystemReady SR, SBSA/SBBR, ACPI/SMBIOS evolution, Redfish schema extensions, and PLDM profile usage; advocate for secure update frameworks (UEFI Capsule, Redfish UpdateService, PLDM FW Update).
Champion resilience features: ECC policies, patrol scrubbing, memory poison handling (CXL/DDR), graceful degradation, RAS policy tuning, and serviceability KPIs valued by hyperscalers.