CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent•Santa Clara, CA

6d•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high-performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post-silicon validation. The ideal candidate has verified complex out-of-order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring-up. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

Deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors.
Strong knowledge of RISC-V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior.
Highly proficient in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies.
Hands-on experience with CPU reference models, instruction generators, ISS-based checking, or differential testing.
Practical expertise with formal verification and large-scale CPU verification environments.

Responsibilities

Own strategy for RISC-V high-performance superscalar CPUs and CPU subsystems.
Drive verification planning for out-of-order, speculative, superscalar microarchitectures.
Build and scale test plans, coverage, checkers, assertions, scoreboards, and constrained-random environments.
Verify key CPU features including frontend, branch prediction, rename, scheduling, execution, load-store, memory ordering, cache hierarchy, retirement, exceptions, interrupts, debug, and coherency interactions.
Work closely with architecture, RTL, performance modeling, SoC, firmware, compiler, and validation teams while mentoring senior engineers and establishing best practices across the CPU verification organization.