CPU Software & Hardware Co-Design Engineer (ML Systems)

Qualcomm • , FL

1d • $177,300 - $265,900

About The Position

Qualcomm Technologies is hiring a CPU Software & Hardware Co-Design Engineer for its Engineering Group. The role sits at the intersection of CPU architecture, machine learning workloads, and system-level performance optimization, with a focus on software–hardware co-design for next-generation QMX architectures. The engineer will work across ML models, low-level kernels, simulation, and architectural feedback to enable efficient execution of machine-learning workloads on CPU platforms.

The position involves characterizing ML workloads, generating execution traces, analyzing performance bottlenecks, optimizing kernels and libraries, and collaborating with CPU architecture and design teams to inform future CPU features. It also includes developing QMX-focused kernels, integrating with ML frameworks, and benchmarking CPU-centric ML performance across hardware generations.

Requirements

• Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field and 8+ years of Software Engineering or related work experience; or a master's degree in one of those fields and 7+ years of related experience; or a PhD in one of those fields and 6+ years of related experience.
• 4+ years of work experience with a programming language such as C, C++, Java, or Python.
• Strong background in computer architecture or systems programming.
• Strong background in machine-learning fundamentals.
• Proficiency in C/C++; C/C++ is mandatory.
• Experience with performance profiling, benchmarking, and optimization.

Nice To Haves

• Experience with QEMU or equivalent simulators.
• Experience developing ML kernels such as GEMM, convolution, and attention.
• Knowledge of CPU architecture, including pipelines, caching, and SIMD/vector extensions such as NEON, SVE, and QMX.
• Familiarity with ML frameworks and inference stacks.
• Experience with low-level optimization, including intrinsics, assembly, and memory and cache tuning.

Responsibilities

• Identify and prioritize ML use cases and models suited to CPU-centric execution, including LLMs, vision, speech, and recommender systems.
• Analyze workload compute intensity, memory bandwidth and cache behavior, parallelism, and dataflow patterns.
• Generate detailed ML workload execution traces using QEMU or equivalent simulators.
• Develop tooling to capture instruction-level execution behavior and extract performance counters and bottlenecks.
• Enable accurate workload behavior modeling for architectural exploration.
• Identify bottlenecks across CPU pipelines, memory hierarchy, and instruction utilization.
• Optimize performance hotspots through kernel-level tuning, algorithmic improvements, and data-layout and memory optimizations.
• Drive measurable improvements in workload performance.
• Collaborate with CPU architecture and design teams, providing data-driven insights from real workloads and proposing architectural enhancements.
• Influence next-generation CPU features in compute units, vector/SIMD extensions such as QMX, and memory subsystems.
• Design and implement highly optimized ML kernels and libraries for QMX architecture, including GEMM, convolution, attention, and activation functions.
• Enable integration with ML frameworks such as PyTorch, ONNX, XNNPACK, and MLAS.
• Apply SIMD/vectorization, cache-aware execution, and parallel execution strategies.
• Optimize CPU-centric ML benchmarks such as Geekbench AI and internal benchmarking suites.
• Establish performance baselines, track improvements across hardware generations, and perform competitive analysis and performance positioning.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior