CPU Power Management and Performance Architect

Intel Corporation•Santa Clara, CA

2d•$164,470 - $311,890•Hybrid

About The Position

Intel is seeking an experienced SoC CPU power-management professional to define and drive power-management architecture for next-generation mobile and desktop client processors. The role owns end-to-end CPU power and performance requirements within the broader SoC, defines architectural features and control mechanisms, and guides implementation from early product definition through post-silicon validation. The architect works with CPU microarchitecture, SoC integration, silicon design, firmware, operating system, validation, thermal, and product teams to advance performance, energy efficiency, and user experience. The position calls for system-level thinking, strong analytical problem-solving, technical leadership, and communication skills. The successful candidate connects design decisions to CPU, SoC, and product outcomes; explores architectural tradeoffs; and expands technical expertise into broader architecture ownership.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6 or more years of relevant experience; or a master’s degree with 4 or more years; or a PhD with 2 or more years.
Within the overall experience, 4 or more years in SoC or IP architecture, CPU or SoC design, microarchitecture, power and performance engineering, or a closely related technical field.
Relevant experience may come from architecture, design, modeling, validation, firmware, or other closely related engineering roles.
System-level thinking and ability to connect detailed design decisions to CPU, SoC, and product-level outcomes.
Strong analytical problem-solving skills, including innovation, feasibility assessment, and disciplined exploration of architectural tradeoffs.
Technical leadership and communication skills to influence CPU architecture, SoC design, firmware, validation, and product roadmaps across organizational boundaries.
Curiosity, initiative, and willingness to develop deep technical expertise into broader architecture ownership.

Nice To Haves

Extensive experience in CPU or SoC design, microarchitecture, architecture, or power and performance engineering; candidates with deep design expertise and system-level leadership ready to grow into an architecture role are encouraged to apply.
Experience designing, integrating, or architecting compute SoCs, CPUs, or complex silicon IP, with understanding of how local design decisions affect system-level power, performance, and product behavior.
Knowledge of CPU or SoC power-management concepts such as DVFS, clock and power gating, idle states, telemetry, thermal constraints, or firmware and operating system interactions.
Advanced knowledge of computer architecture, CPU microarchitecture, system-level design, and interactions among cores, caches, interconnects, memory, accelerators, and platform IP.
Experience with performance or power modeling, benchmarking, workload analysis, functional modeling, statistical analysis, or correlation of model predictions with silicon measurements.
Demonstrated ability to lead technical tradeoffs, communicate across design, architecture, firmware, validation, and product teams, and expand from detailed design ownership to broader architectural decision-making.

Responsibilities

Own power-management and performance architecture for mobile and desktop CPUs as part of the CPU architecture team; define architectural capabilities, develop techniques, guide implementation, and drive energy efficiency across operating conditions and product segments.
Define and analyze CPU power and performance requirements, budgets, and interfaces within the SoC across CPU cores, shared caches, interconnects, memory, accelerators, and platform IP.
Create and maintain workload-based CPU and SoC power and performance models and targets; correlate predictions with pre- and post-silicon data; and use results to improve current implementations and future architectures across idle, sustained, burst, and peak workloads.
Partner with firmware and operating system teams to define CPU and platform power-management capabilities, including DVFS policies, clock and power gating, idle-state management, telemetry, residency, latency, and quality-of-service tradeoffs.
Influence CPU microarchitecture and SoC fabric, memory, and I/O architecture to optimize power efficiency, performance, throughput, latency, and quality of service under representative workloads.
Lead cross-functional architecture and design reviews, drive tradeoff decisions across power, performance, area, cost, thermals, and product experience, and align CPU, SoC integration, validation, firmware, operating system, and product teams.
Translate product usage models and competitive insights into architectural requirements, feature specifications, and measurable success criteria; track execution and communicate risks, decisions, and progress to technical and product leadership.