CPU Memory Design Engineer

Intel Corporation•Austin, TX

1d•$122,440 - $232,190•Hybrid

About The Position

The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a CPU Memory Design Engineer. In this role, you will be responsible for designing, developing, and building full-custom as well as compiler-based SRAMs, Large Signal Arrays (custom multi-ported register file), ROMs, custom memories, digital circuits and Caches for Intel CPU and SOCs. You will be partnering with and leveraging domain experts across various areas of technology development to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on advanced CMOS process technologies for Intel CPU and SOCs. This will be a fast-paced dynamic environment where you will work in the high performance, low power CPU design team on a wide spectrum of circuit activities including, but may not be limited to: - Technical readiness, memory circuit design, characterization and simulations. - Cache design, critical path simulations and design custom blocks to meet stringent Power/Performance/Area constraints. - Memory path-finding activities and power, performance and area (PPA) optimization. - Memory bit-cell and complex periphery IC design and automation. - Memory array/IP design, memory circuit innovation - Methodology definition tasks as well as executing project schedules

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with 4+ years of experience; or Master's degree with 3+ years of experience; or PhD.
Proficiency in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area.
Expertise in Very Large Scale Integration (VLSI) circuits and design methodologies.

Nice To Haves

Experience in low-power implementation techniques and memory design.
Familiarity with circuit and layout trade-offs for optimized design.
Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments.

Responsibilities

Technical readiness, memory circuit design, characterization and simulations.
Cache design, critical path simulations and design custom blocks to meet stringent Power/Performance/Area constraints.
Memory path-finding activities and power, performance and area (PPA) optimization.
Memory bit-cell and complex periphery IC design and automation.
Memory array/IP design, memory circuit innovation
Methodology definition tasks as well as executing project schedules