CPU Integration & 3DIC CAD Engineer

Qualcomm • Santa Clara, CA

23d • $175,600 - $263,400

About The Position

Join the Nuvia/CPU team -- our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. You will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our custom CPUs to have industry-leading power, performance and area.

Requirements

• Bachelors/Masters degree in Electrical Engineering or Computer Science
• Total of 8 years of educational + industry experience
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Nice To Haves

• Ten+ years of hands-on experience in development of high-performance chips - either in a design or CAD role
• Experience with Innovus, Primetime, Star-RC or equivalents
• Experience with advanced technology nodes (5nm or lower)
• High level of programming proficiency (Python and Tcl) and data structures a plus

Responsibilities

• Work closely with worldwide cross-functional teams across design & CAD
• Enablement of 3DIC/multi die in either existing flows or developing new flows
• Implementation/Planning flows (such as TSV’s during floor planning)
• Support Static Timing / Extraction across multiple dies
• Support power integrity flows across multiple chiplets
• Architect, maintain and support these flows, and resolve project-specific issues
• Work with EDA vendors to define roadmap and to resolve tool issues

Benefits

• competitive annual discretionary bonus program
• opportunity for annual RSU grants
• highly competitive benefits package is designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Senior