CPU Design Verification Engineer

Intel•Austin, TX

1d•$122,440 - $172,860•Onsite

About The Position

Join Intel's Silicon & Platform Engineering Group as a CPU Design Verification Engineer on the innovative ATOM team, where you'll be instrumental in developing next-generation, power-efficient processors that define the future of computing. You'll work on cutting-edge CPU architectures that power everything from ultra-mobile devices to edge computing solutions, directly impacting billions of users worldwide. As a CPU Design Verification Engineer, you'll play a pivotal role in ensuring the functional correctness and performance of Intel's ATOM processor family. Working alongside world-class CPU architects, RTL designers, and physical design teams, you'll help validate designs that meet rigorous functional, performance, and power efficiency goals. This is your opportunity to tackle complex technical challenges while contributing to products that shape the computing landscape.

Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 1+ years of relevant experience. Or a PHD in the same field.
1+ years of experience in hardware modeling languages such as Verilog, VHDL, or SystemVerilog, and industry-standard simulation tools.
Experience developing UVM-based testbenches for reusable and scalable verification environments.
Programming skills in at least one language such as Python, Perl, or C++.
Computer architecture fundamentals, with emphasis on CPU microarchitecture.
Experience in debugging and validation, including functional coverage analysis, test development, and root cause analysis.
Strong analytical and problem-solving skills.
Clear verbal and written communication.
Ability to collaborate across diverse teams and disciplines.
Adaptability in a fast-paced, evolving technical environment.
Ownership mindset with attention to detail.
Continuous learning and curiosity for new technologies.
Ability to work independently while contributing effectively to a team.

Nice To Haves

Knowledge of x86 architecture, Intel Architecture ISA, and assembly programming.
Experience in pre-silicon and post-silicon CPU verification, debugging, and analysis, including identifying and closing coverage gaps.
Familiarity with software validation techniques such as microcode, firmware, or low-level code generation.
Experience using industry-standard simulation tools like Synopsys VCS and version control systems such as Git.
Demonstrated technical ownership in CPU microarchitecture, design, or verification with hands-on expertise.
Innovative application of AI or automation to enhance verification processes and accelerate validation timelines.

Responsibilities

Lead Comprehensive CPU Verification: Develop and execute sophisticated verification plans to validate CPU logic against architectural and microarchitectural specifications.
Create scalable, reusable verification environments using UVM-based testbenches and advanced functional coverage models.
Perform in-depth functional coverage analysis, identify critical verification gaps, and implement strategic closure plans.
Drive Technical Excellence Through Innovation: Execute complex system-level simulations to validate functionality, power consumption, and timing characteristics.
Debug and perform root-cause analysis of issues in pre-silicon environments, implementing robust corrective measures.
Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize verification workflows.
Collaborate for Maximum Impact: Partner closely with CPU architects, RTL developers, and physical design teams to verify complex architectural features.
Maintain and enhance verification infrastructure, methodologies, and automation flows to maximize team productivity.
Document comprehensive verification strategies and lead technical reviews with cross-functional stakeholders.
Contribute to CPU architecture and microarchitecture feature definition to achieve optimal functional, performance, and power targets.