CPU Core Physical Design Technical Graduate Intern, Spring

Intel Corporation•Folsom, CA

3d•$105,698 - $105,702•Hybrid

About The Position

As a 2027 Physical Design Engineering Graduate Intern, you will contribute to the physical implementation of silicon designs to create manufacturing-ready solutions. Your day-to-day work will involve tasks such as synthesis, place and route, timing analysis, clocking, and/or integration. By assisting in verification and signoff activities, you will ensure manufacturability and performance compliance, directly supporting Intel's broader innovation goals. The Data Center Group (DCG) is at the forefront of transforming data-centric technologies by delivering solutions that power Intel's silicon and platform advancements. Focused on high-performance computing, storage, and connectivity, DCG plays a vital role in shaping Intel's impact across industries, enabling scalable, automated, and impactful designs for modern infrastructure challenges. This internship is scheduled from January 2027 to August 2027. The ideal candidate is local to the Folsom area or will arrange for a semester away. Relocation is available.

Requirements

Pursuing a Master's degree in Electrical Engineering (EE), Computer Engineering (CE), or a related field.
Coursework, academic projects, or research experience in digital integrated circuit design and VLSI physical design.
Fundamental knowledge of logic synthesis, place and route, and static timing analysis (STA).
Experience with one or more scripting/programming languages such as Perl, Tcl, or Python.
Understanding of semiconductor design flows and ASIC/SoC implementation concepts.

Nice To Haves

Experience with synthesis, place and route, and timing analysis.
Knowledge of low-power design techniques and PPA optimization.
Programming experience with Perl, Tcl, and/or Python.
Familiarity with ASIC/SoC physical design flows and EDA tools.
Experience from coursework, research, or projects in VLSI or semiconductor design.

Responsibilities

Support physical design implementation, including synthesis, place and route, and integration.
Conduct timing analysis and clocking to optimize design performance.
Assist in verification and signoff activities to ensure manufacturability and compliance.
Collaborate with cross-functional teams to enhance design scalability and automation.
Learn and apply knowledge through hands-on tasks and projects aligned with Intel's goals.