Battery/ Pack Systems Engineer

QuantumScape Corporation•San Jose, CA

7h•Onsite

About The Position

QuantumScape is seeking a Battery/Pack Systems Engineer to join their team. This role is central to the development of an integrated PSU+ BBU rack power shelf for hyperscale AI data centers. The engineer will be responsible for all aspects of the battery pack, from cell integration to safety and cycle life validation. This position requires close collaboration with various engineering teams, including power electronics, firmware, and thermal-mechanical engineers, and is critical for ensuring the safety and longevity of solid-state batteries in data center applications.

Requirements

8+ years in battery pack/module design with at least one product through prototype validation or production.
Hands-on BMS hardware architecture experience (specifying topology and component selection).
Cell characterization and modeling skills (impedance spectroscopy, capacity fade analysis, thermal characterization).
Experience with battery safety standards, specifically UL 1973.
Proficiency with pack-level thermal modeling and mechanical design (SolidWorks, Creo, or equivalent).
Comfortable working with evolving cell specs and making design decisions under incomplete data.

Nice To Haves

Prior exposure to solid-state, lithium-metal, or other next-generation cell chemistries.
Experience with data center, telecom, or stationary storage backup battery systems.
Familiarity with electrochemical modeling tools (COMSOL, PyBaMM, AutoLion, or equivalent).
Experience with IEC 62619 industrial battery safety standard.
Background in applications engineering at a cell manufacturer.
Knowledge of functional safety principles (IEC 61508 or equivalent).

Responsibilities

Design the cell-to-pack mechanical assembly, including cell stacking, compression systems, interconnects, and structural integration.
Architect the BMS hardware topology and specify component selection, protection FET sizing, sense line routing, and communication interfaces.
Develop and tune state-of-charge and state-of-health estimation algorithms tailored to solid-state cell electrochemistry.
Co-develop charge/discharge profiles with the firmware engineer, optimizing for data center duty cycles.
Design the thermal interface between cells and enclosure in collaboration with the thermal-mechanical engineer.
Conduct pack-level FMEA and safety analysis, and execute abuse test protocols.
Design accelerated aging test protocols for data center-specific duty cycles.
Serve as the primary liaison to the cell development team, translating pack-level requirements into cell-level specs and providing feedback.
Support UL 1973 and UL 9540A safety certification activities.