Back End( BE) Process Integration Engineer

Intel Corporation•Hillsboro, OR

2d•$103,730 - $170,630•Onsite

About The Position

As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. The Intel Logic Technology development (LTD) organizations deliver process technology innovation to drive Intel's product roadmap.

Requirements

PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or a closely related semiconductor field of study.
Hands-on cleanroom experience in one or more of the following: Interconnect process development (BEOL integration), Advanced interconnect metallization (Cu, Co, Ru, Mo, or emerging metals), Electrical characterization of interconnect stacks (RC, EM, reliability), Cleanroom process development in a university or industry fab environment.

Nice To Haves

Deep understanding of RC delay, electromigration, TDDB, via resistance, and low-k dielectric integration
JMP, Python (scripting/automation), SQL, MATLAB, JSL, TCL — used for real data analysis, not just familiarity
Hands-on experience with dry etch, ALD, PECVD, CMP, metallization in a research or production fab
Demonstrated ability to design experiments, analyze results, and drive process improvements.
Strong analytical and presentation skills — ability to translate complex data into actionable engineering decisions
Familiarity with automation and defect classification systems (e.g., KLA, Applied Materials review tools).
Proven ability to influence outcomes across engineering disciplines without direct authority.
Clear, concise written and verbal communication of complex technical issues to diverse audiences.
Track record of driving projects to completion with accountability in ambiguous, fast-moving environments.

Responsibilities

Develop and define integrated front-end and back-end process flows for new technology nodes.
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, dielectric, and metrology teams.
Optimize RC (resistance-capacitance) performance.
Establish process windows and integration schemes.
Analyze yield loss and parametric failures.
Perform root cause analysis using statistical tools (SPC, DOE, FMEA).
Drive corrective actions to improve yield and cycle time.
Implement control plans and process monitoring strategies.
Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis
Ensure margins for electromigration, stress migration, TDDB, time dependent via degradation.
Evaluate impact of process window shifts on reliability.
Support ramp from R and D to high-volume manufacturing (HVM).
Document process specifications and standard operating procedures (SOPs).