Associate Fellow - Design

Microchip Technology Inc.•San Jose, CA

2d•Onsite

About The Position

Microchip’s Data Center Solutions Business Unit (DCS) offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Associate Fellow, Design Engineering you will provide leadership in the highly successful PCIe Switch product line. These complex 800M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments. As a Associate Fellow, Design Engineering, your job will entail the following: Oversite of complex digital integrated circuits at the block, subsystem or device level, which are coded in Verilog, System Verilog Translate complex architectural requirements into microarchitecture that is realizable in targeted technology node Lead and mentor 3-4 fellow design engineers; scope and schedule deliverables Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems Communicate with architects to justify design implementation decisions and associated trade-offs Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds Become versed in applicable storage and computer interface protocol standards

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
15+ years related experience
RTL Design - Experience in RTL design using System Verilog, Verilog is required.
Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
Scripting and programming skills using csh, bash, perl, python, tcl, etc.
Excellent analytical and debugging skills and the ability to proactively solve issues
Experience with integration of 3rd party IP.
Experience with integration of high-speed, mixed signal IP
Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.
Excellent knowledge in logic synthesis and static timing analysis.
Worked with physical design teams for layout implementation.
Familiar with low power methodology and flows.
Capable of debugging EDA tool issues or design related issues.
Working knowledge of DFT.
Good verbal and written communication skills
Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

Nice To Haves

Protocol knowledge and experience in PCI-Express will be an asset
Knowledge of AHB/AXI bus protocols is desired.
Experience with Formal Verification a plus.

Responsibilities

Oversite of complex digital integrated circuits at the block, subsystem or device level, which are coded in Verilog, System Verilog
Translate complex architectural requirements into microarchitecture that is realizable in targeted technology node
Lead and mentor 3-4 fellow design engineers; scope and schedule deliverables
Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
Communicate with architects to justify design implementation decisions and associated trade-offs
Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
Become versed in applicable storage and computer interface protocol standards