Associate, Electrical Engineering
About The Position
Reporting to the Manager, Engineering (ASIC/FPGA), the engineer will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Requirements
- Pursuing a Bachelor’s Degree in Engineering, Engineering Technology (Chemistry, Physics, Mathematics, Data Science, or Electrical/Electronics/Computer Engineering/Computer Science) or have completed their Bachelor’s degree within the last 12 months, regardless of age.
- Hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols.
- Experience with RTL (VHDL)
- Experience with Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
- Experience with Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
- Experience with verification test plans and End to End Simulations
- Experience supporting FPGA bring up
- Experience validating design through HW/SW integration test with test equipment
Nice To Haves
- Experience with Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework
- Experience with Synopsys (DC/Primetime/Synplify)
- Experience with Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus)
- ASIC front end capability
Responsibilities
- Derive FPGA design specifications from system requirements
- Develop detailed FPGA architecture for implementation
- Implement design in RTL (VHDL) and perform module level simulations
- Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
- Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
- Generate verification test plans and perform End to End Simulations
- Support Board, FPGA bring up
- Validate design through HW/SW integration test with test equipment
- Support product collateral for NSA certification
Benefits
- relocation stipend
- 401(k)
- EAP
- company-paid holidays
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
