ASIC Physical Design Principal Engineer
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Requirements
- Bachelor’s degree in Engineering and 15+ years of ASIC related experience, Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.
- Experience developing and driving methodologies in the area of Power Optimization and Analysis.
- Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
- Experience working with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.
Nice To Haves
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
- Experience in Fullchip floor-planning and power grid planning.
- Experience with custom clock (H-Tree or Mesh) at chip level.
- Experience with Python, TCL, or Perl programming.
Responsibilities
- RTL-to-GDSII implementation, including Logic Synthesis, Hierarchical Floorplanning, Place and Route, Static Timing Analysis, Power Integrity, and Equivalence checks with a focus on Power, Performance and Die-Size Optimization.
- Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
- Work closely with RTL, DFT, Implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
- Guide Clock Tree Synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
- Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
- Complete Functional and Timing ECO implementation using industry-standard flows and contribute to automation for STA methodology.
- Evaluate multiple timing methodologies/tools across different technologies and design types.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt employees)
- flexible vacation time off program (exempt employees)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Principal
