ASIC Packaging Signal/Power Integrity Engineer (Hybrid)
About The Position
We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms. This role involves developing, documenting, and implementing design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products. The engineer will analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB. Additionally, the role includes designing, documenting, and developing ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. Collaboration with system partners, vendors, and design leads is essential to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Requirements
- Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience.
- Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
- Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Nice To Haves
- Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
- Experience with die-to-die interfaces (UCIe or proprietary).
- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
- Working knowledge of Vector Network Analysis.
- Basic knowledge of IBIS.
Responsibilities
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (non-sales roles)
- performance-based incentive pay (sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
