ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA • Santa Clara, CA

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About The Position

We are now looking for a ASIC Floorplan Design Engineer - NCG. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Requirements

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Experience in Verilog, System Verilog or similar HVL
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience

Nice To Haves

• Experience in driving development of large scale ASIC floorplan is a huge plus.

Responsibilities

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Benefits

• equity
• benefits

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level