ASIC Engineer Intern

Hewlett Packard Enterprise•Sunnyvale, CA

7d•$35 - $46•Onsite

About The Position

Join our ASIC team as an intern and gain hands-on experience in cutting-edge semiconductor development. Interns will have the opportunity to focus on one of three specialized areas—ASIC Design, ASIC Verification, or ASIC Tools & Methodologies—based on their interests and skills. You are not expected to perform all three activities; instead, you will work closely with senior engineers in your chosen domain.

Requirements

Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Coursework in Digital Logic Design, Computer Architecture, or VLSI Design is highly desirable.
Familiarity with ASIC concepts through academic projects or internships is a plus.
Exposure to SystemVerilog, UVM, and basic knowledge of Python, C++, or similar languages.
Understanding of ASIC design flow, verification methodologies, and EDA tools for physical design.
Strong analytical and problem-solving skills.
Excellent communication and interpersonal skills.
Ability to manage time and meet deadlines.
Passion for high-tech and continuous learning.

Nice To Haves

Knowledge of networking protocols, machine learning, or advanced computer architecture is a plus.

Responsibilities

Participate in ASIC architecture investigation tasks, including evaluating design trade-offs and performance analysis.
Create detailed functional and micro-architectural specifications
Assist in RTL design using SystemVerilog, ensuring functionality, performance, and power goals.
Support synthesis, linting, and design reviews.
Develop and maintain testbenches using SystemVerilog and UVM.
Write test plans, assertions, create functional coverage models, and debug simulation failures.
Contribute to regression setup and results analysis.
Participate in emulation activities for pre-silicon validation.
Contribute to automation to accelerate ASIC development processes, flow improvements, and EDA tool evaluations.
Develop utilities to enhance productivity and improve design/verification processes.
Work with EDA tools for physical design, including synthesis, place-and-route, timing analysis, and sign-off flows.
Support Design-for-Test (DFT) methodology development and integration.
Collaborate with team members to troubleshoot technical issues and propose solutions.
Participate in team meetings, learn project methodologies, and share progress during periodic reviews.
Actively engage in learning new technologies and best practices relevant to your focus area.
Complete assigned tasks efficiently and incorporate feedback.