ASIC DFT Technical Lead

Cisco•San Jose, CA

1d•Onsite

About The Position

You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA, involved in crafting cutting edge next generation networking chips. As the lead, you will drive the DFT/DFx and quality process through the early product life cycle, including architecture definitions, RTL implementation, and quality checks. Your engagement will also extend to the development of flow/methodologies, test plans, tape-out sign-off requirements, post silicon validation, and production yield & DPPM support. At Cisco, the company is revolutionizing how data and infrastructure connect and protect organizations in the AI era, innovating for 40 years to create solutions that power human and technology collaboration across physical and digital worlds. These solutions provide unparalleled security, visibility, and insights across the entire digital footprint. Fueled by technology, Cisco experiments and creates meaningful solutions, offering limitless opportunities for growth and building within its worldwide network of experts. The company emphasizes teamwork and collaboration with empathy to achieve global impact.

Requirements

Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10+ years of ASIC Hardware Development experience.
Prior experience on hardware design specifications and verification plan/matrix, RTL & testbench implementations.
Prior experience on Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Post-silicon test bring up and debug experience; Ability to analyze and root cause test failures on silicon.
Prior experience on RTL QA checks, including lint & CDC

Nice To Haves

Scripting skills: Tcl, Python/Perl.

Responsibilities

Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead a team of engineers to deliver expected implementations on schedule.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses subject to Cisco’s policies (for non-sales roles)