ASIC Engineering Technical Leader

Cisco • San Jose, CA

6d

About The Position

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact
Participate in and contribute to chip architecture definition and discussions.
Author design specifications and participate in micro-architecture specification reviews.
Implement Verilog RTL to meet timing and performance requirements.
Help define, evolve, and support our design methodology.
Mentor junior engineers on performing project tasks and problem solving.
Collaborate with the verification team to address design bugs and close code coverage.
Work closely with physical design team to close design timing and place-and-route issues.
Triage, debug, and root cause simulation, software bring-up, and customer failures.
Perform diagnostic and post silicon validation tests in the lab.

Requirements

• Bachelor’s degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or Master’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience.
• Verilog/System Verilog programming experience.
• Interactive and waveform debug experience.
• Experience resolving setup and hold timing violations with RTL modification.
• Experience developing micro-architecture solutions and RTL implementation.

Nice To Haves

• Experience with digital design principles and microarchitecture concepts such as buffering and scheduling architectures.
• Experience with design quality checks including CDC (Clock Domain Crossing) and Spyglass static analysis.
• Scripting experience (Python, Perl, TCL, shell programming).

Responsibilities

• Participate in and contribute to chip architecture definition and discussions.
• Author design specifications and participate in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Help define, evolve, and support our design methodology.
• Mentor junior engineers on performing project tasks and problem solving.
• Collaborate with the verification team to address design bugs and close code coverage.
• Work closely with physical design team to close design timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post silicon validation tests in the lab.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees