ASIC Physical Design Technical Lead

Cisco • San Jose, CA

1d

About The Position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. This role involves fullchip floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints. It requires collaboration with system and package design teams, hierarchical implementation flow, RTL-to-GDSII implementation with a focus on performance, power and die size optimization. The role also includes analyzing existing tool flows, working with various teams and vendors, and proficiency in low-power design methodologies using UPF.

Requirements

• Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience.
• Experience working on Fullchip activities.
• Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Nice To Haves

• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Fullchip floor-planning and power grid planning.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts

Responsibilities

• Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
• Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods
• RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
• Proficiency in low-power design methodologies using UPF
• Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams
• Experience in using AI tools to improve productivity

Benefits

• medical, dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• grants of Cisco restricted stock units
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• paid year-end holiday shutdown
• 4 paid days off for personal wellness determined by Cisco
• 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (for non-exempt employees)
• flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (for exempt employees)
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• annual bonuses (for non-sales roles)
• performance-based incentive pay (for sales plans)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior