ASIC Engineering Technical Leader

Cisco•San Jose, CA

About The Position

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products, including DSP ASICs, silicon photonic PICs, and coherent modules, to accelerate network scalability through advancements in performance, capacity, and cost. These products empower cloud and service providers to meet the fast-growing demand for data. Cisco is recognized as a top workplace globally. The company is seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with a focus on Design-for-Test (DFT). In this role, the leader will be responsible for developing DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products. Cisco aims to revolutionize how data and infrastructure connect and protect organizations in the AI era, creating solutions that power how humans and technology work together across physical and digital worlds, providing unparalleled security, visibility, and insights.

Requirements

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior experience working with ASICs
Prior experience in scan insertion and DFT setup, integration and validation
Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.

Nice To Haves

10+ years of experience working with ASICs
10+ years of experience in scan insertion and DFT setup, integration and validation
Experience driving ASIC DFT execution from concept through tapeout
Experience working with ATE testers and test teams
RTL experience to understand and debugging issues pertaining to DFT
Ability to solve complex problems including clock domain crossings
Familiar with advanced silicon process and technology nodes for high speed and low power consumption
Strong implementation or integration of design blocks using Verilog/System Verilog

Responsibilities

Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent, or Synopsys, tools for RTL and gate netlist DFT implementation.
Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post-silicon testing and validation support
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (for non-exempt employees)
flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (for exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales plans)