ASIC Design Verification Engineer
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.
Requirements
- Bachelor’s degree in Electrical or Computer Engineering and 2+ years of ASIC experience or Master's degree in Electrical or Computer Engineering and 0+ years of experience.
- Experience in System Verilog and UVM methodology
- Experience building reusable and scalable test benches from scratch
- Experience with scripting using Perl and/or Python
Nice To Haves
- Experience with forwarding logic, parsers, or P4
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
- Experience with formal verification tools (e.g., IEV or VC Formal)
- Experience in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP
Responsibilities
- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
- Build DV environments from scratch for block and cluster levels
- Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus
- Ensure comprehensive verification coverage through code and functional coverage implementation and review
- Qualify RTL design by running Gate Level Simulations on netlists
- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration
- Support design testing in emulation environments
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
