ASIC Design Verification Engineer

Qualcomm•Santa Clara, CA
•$113,000 - $169,600

About The Position

Qualcomm Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We're focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros' teams deliver cutting-edge products across every established wireless standard/protocol. We are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver.

Requirements

  • Bachelor's degree in Science, Engineering, or related field.
  • RTL Design
  • ASIC front-end experience
  • Scripting Languages knowledge (e.g. Perl or Python)

Responsibilities

  • Participating in development of leading-edge ASICs for multi-function mobile platforms.
  • Working with engineers or developing unit-level and integrated-level test benches.
  • Assisting in synthesis and gate-level simulation tasks related to your module.
  • Assisting with timing of the entire chip.
  • Leveraging knowledge of wireless LAN, Bluetooth, and RF transceiver.

Benefits

  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Highly competitive benefits package
Ā© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service