ASIC Design Manager

Ralliant•Boulder, CO

3d•$148,900 - $276,500•Hybrid

About The Position

Tektronix is seeking an ASIC Design Manager to lead and grow its digital ASIC design and realization organization. ASICs are central to Tektronix’s next-generation instrumentation platforms. This role is responsible for the complete ASIC flow, from architecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up. This is a hands-on leadership role that combines people management, vendor relations, technical direction, and project execution. The manager will lead engineers responsible for digital design, verification, and physical implementation while remaining engaged in critical architecture, implementation, timing closure, power integrity, and signoff decisions. The successful candidate will possess strong experience in ASIC development and the ability to guide a multidisciplinary team through complex technical and program challenges.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience.
Significant experience developing ASICs or complex digital integrated circuits, including digital design and physical implementation activities.
Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary engineering teams.
Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.
Experience with physical design and implementation, including several of the following: floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.
Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.
Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.
Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release.
Strong communication, collaboration, organizational, and problem-solving skills, with the ability to work effectively across engineering, product, and program-management teams.

Nice To Haves

Experience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning.
Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field.
Experience leading end-to-end digital ASIC or SoC implementation through tapeout.
Experience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications.
Experience with multi-mode, multi-corner timing analysis; signal-integrity analysis; IR-drop and electromigration verification; or other physical signoff methodologies.
Experience optimizing designs for performance, power, area, yield, reliability, and manufacturability.
Familiarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or other advanced packaging technologies.
Experience with FPGA prototyping, emulation, or other pre-silicon validation methods.
Experience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers.
Experience improving ASIC development methodologies, automation, and team execution practices.

Responsibilities

Lead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers; establish clear priorities, support career growth, and foster a collaborative engineering culture.
Own the end-to-end digital ASIC development flow, including microarchitecture, RTL development, IP selection and integration, synthesis, constraints development, floorplanning, clock-tree synthesis, place-and-route, timing closure, and tapeout.
Set technical direction for digital IP, subsystem design, full-chip integration, and physical implementation, balancing performance, power, area, reliability, reuse, cost, and schedule.
Drive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure.
Have knowledge of digital-on-top development flows for mixed-signal designs.
Oversee signoff activities, including static timing analysis, signal integrity, power integrity, IR-drop analysis, electromigration analysis, formal equivalence, DRC, LVS, and tapeout-readiness reviews.
Partner with product and system architects to translate product requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets.
Coordinate execution across functional UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams.
Collaborate with package design and process-technology teams on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration.
Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestone tracking, and risk mitigation.
Drive design quality through disciplined methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria.
Improve design flows, automation, and engineering practices to increase productivity, quality, reuse, and schedule predictability.
Support silicon bring-up, characterization, post-silicon debug, and production-readiness activities.
Recruit and retain engineering talent, and manage contractors, external design-service providers, IP vendors, and other technical partners as needed.
Contribute directly to technical reviews and critical design or implementation work when it helps accelerate the team or reduce project risk.

Benefits

Innovation starts with our customers.
Engineering culture is collaborative, technically rigorous, and committed to innovation, continuous learning, and professional growth.
Opportunity to shape the future of Tektronix instrumentation platforms.
Lead a talented engineering team responsible for strategic silicon development.
Influence technology direction, engineering methodology, and program execution.
Help deliver ASIC solutions that enable the next generation of test and measurement innovation.
We believe that cultivating a deeper sense of loyalty and belonging is key to how we attract and retain our best people.
Inclusion & Diversity vision: We Are More Together.
Great places where our teams work and thrive.
Realize your true potential at Tektronix – join us in revolutionizing a better tomorrow!