ASIC Design Engineer - New College Grad 2026

NVIDIA•Santa Clara, CA

1d•$100,000 - $189,750

About The Position

We are now looking for a Logic Design Engineer. As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect network, coherency and last-level caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Requirements

Recent graduate with a BS or MS Degree in Electrical Engineering, Computer Engineering or Computer Science (or equivalent experience).
Experience in processor or other related high performance semiconductor designs.
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
Effective communication and interpersonal skills are required along with the work in a dynamic, global team.
A strong background in computer architecture, cache coherency or high speed interconnects.

Nice To Haves

Your successful track record of mentoring junior engineers and interns a huge plus.

Responsibilities

Crafting and timely delivery of a specific unit on the chip.
Writing readable high performance and low power RTL.
Synthesis and Timing closure.
Design documentation.
Collaborate with our verification team to verify the correctness of your unit.
Work with implementation to achieve your timing, area, performance and power goals.
Assist with timing closure of super units.