Methodology Developer

Capgemini•Brisbane, CA

20h•Onsite

About The Position

In this role, you will help shape and evolve ASIC CAD and EDA methodologies used to deliver complex designs on advanced process technologies. You will collaborate with design, layout, and physical implementation teams to improve tools, flows, and signoff practices that directly impact silicon quality, performance, and time‑to‑market.

Requirements

8+ years of experience in analog and mixed‑signal layout design using deep submicron CMOS technologies, including 3+ years of recent experience on advanced nodes such as FinFET.
Strong understanding of ASIC/SOC CAD flows and signoff methodologies, including timing, power, IR, and physical verification.
Proficient in SKILL and Perl, with a solid foundation in software development
Hands‑on experience with EM/IR analysis, DRC/LVS/PEX/ERC, and working through signoff and waiver processes.
Familiar with circuit design fundamentals, including device characteristics, SPICE and Verilog netlists, and simulation concepts.
Experience using industry‑standard EDA tools such as Synopsys ICC/ICC2 and Cadence Innovus/Virtuoso in UNIX/Linux environments.
Demonstration of strong communication and collaboration skills, enabling you to work effectively across engineering disciplines and influence technical outcomes.

Nice To Haves

Python experience is a plus.

Responsibilities

Influence and evolve ASIC / SoC CAD tools, flows, and design methodologies across design construction, optimization, and sign‑off
Support block‑level and full‑chip integration, enabling high‑quality, production‑ready layouts
Drive sign‑off closure, including timing (SI and OCV), power, IR, and physical verification at block and chip level
Interpret and resolve DRC, LVS, ERC, and PEX results efficiently to meet program schedules
Apply strong knowledge of constraints, timing fixes, and SI prevention techniques
Partner with design and layout teams to meet performance, area, power, and reliability targets
Leverage design automation, scripting, and UNIX environments to improve flow robustness and productivity