ASIC Board Design Engineer – System Lead, PCB Layout, Signal Integrity, and System Architecture (Onsite)
About The Position
Cisco Silicon One develops high-performance ASICs and networking systems for routers, data centers, service providers, and enterprise networks. The Cisco Service Provider Routing Hardware Engineering team designs next-generation Cisco 8000 Series routers powered by Cisco Silicon One ASICs. The position collaborates with board design, ASIC, signal integrity, power, software, mechanical, thermal, manufacturing, systems, and supplier teams to define, design, validate, and release networking products. As a Senior Technical Lead Hardware Board Design Engineer, this individual-contributor role provides enterprise-level technical influence without people-management responsibility. The engineer shapes multi-year hardware architecture, design standards, and technical strategy for major networking products; leads cross-functional initiatives from concept through release and customer delivery; and resolves complex architectural, signal-integrity, power-integrity, reliability, field, and manufacturing challenges. The role also establishes reusable design and verification practices, guides senior engineers, represents hardware engineering in executive and supplier discussions, and recommends investments in future hardware capabilities. The position requires living within commuting distance of Cisco’s Milpitas, California office and commuting to the lab five days per week.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering and 11 or more years of experience; or a master’s degree in Electrical Engineering or Computer Engineering and 7 or more years of related experience; or a Ph.D. in Electrical Engineering or Computer Engineering and 4 or more years of related experience.
- Experience in hardware board design and system architecture, taking high-performance systems from concept through production, including PCIe, Ethernet, DDR, SerDes, and advanced thermal and EMI management.
- Experience with high-speed digital design, signal and power integrity, power distribution, and reliability testing.
- Hands-on experience using Cadence design tools and advanced laboratory instrumentation such as oscilloscopes and logic or spectrum analyzers.
- Experience leading complex, multi-site, cross-functional engineering initiatives.
- Experience partnering with silicon vendors and contract manufacturers to solve high-impact, ambiguous technical challenges at scale.
- Must live within commuting distance of the Milpitas, California office and commute to the lab five days per week.
Nice To Haves
- Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, multi-gigabit SerDes, and advanced packaging.
- Experience in co-packaged or near-packaged optics, signal and power integrity budget analysis, ultra-high-speed signaling, and next-generation power delivery.
- Hands-on experience with Cadence Concept or Allegro, HyperLynx, ANSYS, Keysight ADS, and advanced lab equipment such as VNA, TDR, high-bandwidth oscilloscopes, and protocol analyzers.
- Experience creating Python test scripts to streamline validation and design tasks.
- An analytical, methodical approach to decomposing complex issues, evaluating empirical evidence, and documenting clear, actionable conclusions.
- History of working effectively within cross-functional teams to drive initiatives forward.
- History of influencing senior technical and business leaders across organizational boundaries, with exceptional written, verbal, and executive-level communication skills.
- Commitment to mentoring senior engineering talent.
- Record of delivering large-scale products and technical innovations, demonstrated through patents, influential publications, and active standards participation.
- Strategic thought leadership and commitment to advancing the field.
- Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Responsibilities
- Define long-term hardware architecture, power-delivery strategy, design standards, and technology roadmaps for high-performance networking systems.
- Lead major, multidisciplinary hardware initiatives from early concept through product release and customer delivery.
- Serve as a senior escalation point for novel or high-risk architectural, signal-integrity, power-integrity, reliability, field, and manufacturing issues.
- Develop and communicate technical strategies that align multiple business units and engineering disciplines.
- Establish reusable methods, constraints, verification practices, and quality standards for board design.
- Guide senior engineers and technical leaders through architecture reviews, design tradeoffs, and complex investigations.
- Represent hardware engineering in executive reviews, strategic supplier discussions, standards activities, and selected external technical engagements.
- Anticipate industry and technology shifts and recommend investments in future hardware capabilities.
- Drive decisions using simulations, laboratory evidence, product data, and an understanding of business impact.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays
- Floating holiday for non-exempt employees
- Paid day off for employee’s birthday
- Paid year-end holiday shutdown
- Paid personal wellness days
- Flexible vacation time off for eligible exempt employees
- Paid vacation time for non-exempt employees
- Sick time off
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses for eligible non-sales roles
- Cisco restricted stock unit grants may be available to eligible employees
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
