ASIC Analog Senior Layout Engineer

Cisco•Carlsbad, CA

17h

About The Position

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. As a Senior Layout Engineer on the Silicon One Optics team, you won’t just be drawing polygons—you’ll be architecting the physical blueprint for the world’s fastest optical interconnects. You will own block-to-top integration for next-gen 100G, 200G, and 400G per lambda architectures, pushing silicon past standard limits. From initial floorplanning to sign-off tapeout and silicon bring-up, your physical design decisions will directly power the future of global AI and data center infrastructure.

Requirements

Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
Prior experience supporting block-level layout efforts through tapeout
Prior experience in physical verification and custom layout design, specifically with custom analog layout experience in FINFET 7nm, 5nm, or 3nm
Prior experience with Cadence Virtuoso or similar custom layout tools

Nice To Haves

Prior experience in device-level layout techniques (matching, symmetry, shielding, common-centroid, interdigitation, guard rings, isolation structures) and critical design concepts including parasitic control, thermal management, and signal integrity.
Custom analog experience in TSMC 2nm or below is a plus.
Prior experience with EDA tools like Cadence Virtuoso and Calibre (or equivalent) in a Linux environment, with a strong command of physical signoff flows including DRC, LVS, ERC, parasitic extraction, and EM/IR analysis.
Prior experience with ASIC/SoC tapeout processes and scripting capabilities (Python, Perl, or TCL) for layout automation.
Prior experience working with cross-functional teams across multi-location teams.

Responsibilities

Power Next-Gen Optics: Directly build and optimize complex analog and mixed-signal layouts for groundbreaking 100G–400G/lambda optical solutions.
Own the Silicon Lifecycle: Drive full-flow execution from concept and floorplanning through post-layout extraction, sign-off, tapeout, and post-silicon bring-up.
Solve High-Speed Challenges: Master complex parasitic, signal integrity, and thermal tradeoffs alongside world-class circuit design, packaging, and CAD teams.
Set the Standard: Shape design methodologies, mentor rising engineering talent, and raise the bar for physical execution across the group.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year
plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses
performance-based incentive pay