Applications Engineer, Senior Engineer

Synopsys•Austin, TX

11d•$95,000 - $142,000•Onsite

About The Position

SYNOPSYS IS THE LEADER IN ENGINEERING SOLUTIONS FROM SILICON TO SYSTEMS, ENABLING CUSTOMERS TO RAPIDLY INNOVATE AI-POWERED PRODUCTS. WE DELIVER INDUSTRY-LEADING SILICON DESIGN, IP, SIMULATION AND ANALYSIS SOLUTIONS, AND DESIGN SERVICES. WE PARTNER CLOSELY WITH OUR CUSTOMERS ACROSS A WIDE RANGE OF INDUSTRIES TO MAXIMIZE THEIR R&D CAPABILITY AND PRODUCTIVITY, POWERING INNOVATION TODAY THAT IGNITES THE INGENUITY OF TOMORROW. You have spent years in the verification trenches, debugging mismatches and building flows that hold up when the design scales. The difference between a verification environment that catches bugs and one that creates them is something you feel in your bones, and you have learned to spot the weak points before they become customer escalations. You are equally comfortable sitting with an R&D team discussing simulator architecture and walking a customer through a UVM testbench issue that is blocking their tape out. When a customer says "it worked yesterday," you do not panic. You ask three clarifying questions, pull logs, and usually find the answer in the delta between tool versions or an edge case no one thought to test. You think in terms of deployment success, not just feature lists. A tool is only as good as the customer's ability to use it, and you take ownership of that entire arc. You do not wait for perfect documentation. You read code, you experiment, you build proof of concepts, and you bring solutions that work. At Synopsys, you will work on VCS deployments that directly affect whether chips tape out on schedule, and you will have the technical depth and customer access to make that difference real.

Requirements

Bachelor's in Electronics or Computer Engineering with 5+ years of experience, or Master's with 3+ years, focused on digital design verification
Deep hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and strong understanding of event-driven simulation internals
Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL, with the ability to read and debug complex testbenches and RTL
Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments
Strong scripting skills in Perl, TCL, Shell, and Make, with the ability to automate workflows and build tooling that improves engineer productivity
Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure

Nice To Haves

Experience with Synopsys tools like Verdi, exposure to low-power simulation, gate-level verification, and functional safety methodologies is a strong plus

Responsibilities

Lead VCS simulation deployments at customer sites, working directly with design and verification teams to integrate the tool into their existing flows and resolve adoption blockers
Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure
Partner with field application engineers and R&D to translate customer pain points into actionable product requirements and validate fixes in real customer environments
Drive competitive evaluations and benchmarking engagements, demonstrating VCS capabilities and building the technical case for adoption
Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows, improve simulation throughput, and reduce manual intervention
Interface with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability based on field feedback
Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows