PLL Design Engineers

Chelsea Search Group•San Diego, CA

20h•Hybrid

About The Position

This role is seeking experienced engineers for three distinct positions: PLL Design Engineer, Analog Design Engineer, and SerDes Design Engineer/Lead. The positions are located in Irvine, California, or remote with some travel to Irvine. The company is looking for individuals with advanced degrees and significant experience in analog and mixed-signal circuit design, particularly in advanced node technologies. Responsibilities span the entire design cycle from architecture and simulation to silicon bring-up, lab validation, and documentation.

Requirements

Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience (for Analog and PLL roles).
Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design (for SerDes role).
Experience in advance cmos design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools) is a must
Knowledge of the fundamentals on electromagnetism, lump models, and high-frequency design
Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks.
Strong communication and documentation skills
Experience in lab bring-up, characterization, and debugging designs that reach out production (for SerDes role).
Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes) (for SerDes and PLL roles).
Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs (for SerDes role).
Proven record of taking high-speed SerDes design to tape-out and volume production (for SerDes role).
Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling

Nice To Haves

Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus

Responsibilities

Clock generation and distribution (VCOs, PLL, clock distribution, etc)
Design of custom passive components, from concept to silicon implementation
Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc)
High-speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).
New techniques for the development of next generation optical transceiver
Silicon bring-up, debug and support
Supervise analog layouts within advanced process nodes
System verification and circuit design spec creation
Team communication and documentation
Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
Define architecture, specifications, and circuit topologies for next-generation SerDes
Design high-performance analog/mixed-signal circuits in advanced node technologies
Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range