Analog Layout Intern
About The Position
As an Analog Layout Engineer Intern with Marvell, you'll be a member of the Central Engineering business group — the center hub that provides IP to all other business units, including Automotive, Storage, Security, and Networking. You'll be part of a small, high-impact analog layout team working alongside global colleagues in Argentina, Singapore, the U.S., and throughout Europe. Marvell's scale gives you the opportunity to learn broadly across engineering disciplines while also diving deep into the details of analog layout on cutting-edge semiconductor technologies. Here, you'll contribute to real products and real tapeouts — not just simulations.
Requirements
- Currently pursuing a Bachelor's in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
- Fundamental understanding of electrical engineering concepts, including analog circuit theory and microelectronics
- Coursework or hands-on experience in analog design, IC layout, or VLSI design — whether through degree coursework, summer programs, or technical training
- Familiarity with CAD tools used for physical IC design (e.g., Cadence Virtuoso, Calibre, or similar EDA tools)
- Strong communication skills with the ability to present technical updates to global teams across different time zones and levels of seniority; fluency in English required
Nice To Haves
- Hands-on experience with physical verification flows including DRC, LVS, ERC, or antenna checks
- Exposure to advanced process nodes (FinFET, 3nm, 2nm) or analog/mixed-signal layout techniques
- Experience with scripting languages such as SKILL, Python, or Tcl for layout automation
- Ability to work independently and manage tasks across multiple concurrent projects with flexibility
Responsibilities
- Translate analog IC schematics into physical layout using Cadence Virtuoso, implementing microelectronic layers that go beyond the schematic level
- Run design rule checks (DRC), layout versus schematic (LVS), and other physical verification flows to ensure design integrity
- Collaborate closely with Analog IC Designers to refine, debug, and iterate on layouts until they meet target specifications
- Participate in regular team meetings and project reviews, presenting progress updates and technical findings to cross-functional global teams
- Contribute to the development of next-generation semiconductor IP across advanced process nodes (e.g., TSMC N2/N3)
Benefits
- medical, dental, and vision coverage
- perks and discounts
- robust mental health resources to prioritize emotional well-being
- paid holidays
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What This Job Offers
Career Level
Intern
