Analog Layout Design Engineer

Intel•Hillsboro, OR

1d•Hybrid

About The Position

Intel is seeking a passionate and skilled Analog Layout Design Engineer to join our diverse and inclusive team. As a critical contributor to our design ecosystem, you will drive the creation and optimization of complex layouts for analog signal circuits, ensuring that our designs meet stringent performance, area, and reliability requirements. Your work will directly impact Intel's cutting-edge technologies, enabling the development of innovative solutions that empower businesses and transform industries. In this collaborative role, you will work with cross-functional teams, including analog circuit design, process technology, and package design, to deliver layouts that are efficient, robust, and aligned with our high standards of excellence. We welcome candidates from all backgrounds who are eager to contribute to groundbreaking advancements while expanding their expertise in layout methodologies.

Requirements

Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field of study with 3+ years of experience. Or a Master’s degree in the same field with 2+ years experience.
Analog device and metal layout fundamentals, including analog/mixed-signal fundamentals
Cadence Virtuoso Layout Suite and Calibre/ ICV DRC for design and verification tasks
CMOS technologies and high-voltage rules
Floor planning and hierarchical layout planning for analog and mixed-signal blocks
Conducting performance verification for layouts and debug layout-related issues

Nice To Haves

Strong understanding of analog layout effects including mismatch, parasitics, IR drop, electromigration (EM), and coupling, and their impact on circuit performance
Apply best practices for common-centroid, interdigitation, and symmetry-based layouts to minimize mismatch and variation
Evaluate and mitigate process variations and gradient effects across sensitive analog blocks
Ensure robust layout through parasitic-aware design, working closely with extraction (xtract/spef) and simulation teams
Debug layout-related issues by correlating LVS, DRC, xtract, and silicon behavior
Optimize layouts for noise isolation, shielding, and signal integrity, especially in mixed-signal environments

Responsibilities

Design complex layouts of analog signal circuits based on detailed design specifications.
Conduct a comprehensive set of design verification checks, including process design rules, electron migration, voltage drop (IR), ESD, and other reliability assessments.
Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical requirements.
Perform floor planning and detailed signal planning for complex analog circuits, ensuring optimization for area, power, reliability, and performance.
Drive the development and implementation of innovative analog layout methodologies to improve productivity and layout quality.
Troubleshoot issues related to design, tools, flows, and methodologies utilized in analog layout design.
Collaborate closely with cross-disciplinary teams to meet design specifications, align on requirements, and negotiate layout tradeoffs.