Analog Design Intern, MS - Summer 2027

Marvell Technology•Santa Clara, CA

2d•$38 - $76

About The Position

The Central Engineering Test Chip Development team provides hardware validation for custom SRAM, logic, I/O, and security circuits across Marvell business units in advanced semiconductor technology nodes. The team designs and develops test chips, establishes laboratory infrastructures for silicon characterization and measurement collection, and partners with custom circuit design teams to conduct detailed circuit analysis that verifies silicon performance and functionality.

Requirements

Currently enrolled in a Master’s Degree in MSEE, MSCE, or a related field with an expected graduation date of Fall 2027 – Summer 2028.
Strong understanding of digital logic circuits, memory architectures, I/O circuits, and semiconductor device physics.
Proven experience in design and development, supported by excellent verbal and written communication skills.
Proficiency in Linux/Unix environments, with strong programming and scripting skills in Perl and Python.
Demonstrated ability to work effectively in cross-functional, multidisciplinary teams to solve complex technical challenges.

Responsibilities

Design and verify test chip experiments using Verilog simulation.
Develop, generate, simulate, and debug Verilog-based test patterns for hardware validation of test chip experiments.
Develop and maintain laboratory environments that support hardware debug, diagnostics, characterization, and measurement data collection.
Create software tools and automation scripts (Perl, Python, and Tcl) for design support, hardware characterization, laboratory measurements, data processing, and results analysis.
Analyze, summarize, document, and present characterization and validation results to engineering teams and stakeholders.