Ambient Compute System Architecture and Power Engineer

Qualcomm•San Diego, CA

2d•$148,300 - $222,500

About The Position

As part of Qualcomm’s Low-Power AI (LPAI) Systems group, this role focuses on performance optimization, data-path and power analysis, and architecture of embedded AI subsystems, with emphasis on XR and ambient use cases. The engineer will drive power-efficient system design and analysis across DSP/AI subsystems by analyzing power-performance trade-offs and enabling optimizations across software and hardware for on-device AI.

Requirements

Experience with embedded processor architectures such as DSPs and NPUs, with understanding of processor power behavior.
Experience working with embedded platforms, RTOS, and performance/power profiling tools.
Strong programming skills in Python for analysis, modeling, and automation.
Solid understanding of memory systems, data movement, bandwidth analysis, and Cache memory strategies.
Strong fundamentals in power modeling, power analysis, and system-level power optimization.
Hands-on experience with power measurement tools, and data analysis techniques
Knowledge of fixed-point implementation and algorithm optimization techniques.
Ability to work across cross‑functional and geographically distributed teams.

Nice To Haves

Experience with Qualcomm DSP and LPAI architectures, SDKs, or internal power tools.
Background in audio, or always-on AI use cases.
Exposure to ML inference workloads and their power-performance characteristics

Responsibilities

Analyze and optimize performance and power of LPAI subsystem (DSP, eNPU, memory) with focus on XR and always-on AI workloads.
Support system integration, benchmarking, and commercialization of LPAI solutions across Mobile, XR, Compute, and IoT platforms.
Perform detailed data-path and memory-access analysis (cache, SRAM, DDR) to identify bottlenecks impacting performance efficiency.
Drive ambient system workload partitioning, software optimizations, clock/BW voting, and data reuse strategies.
Collaborate with HW, SW, and PdM teams to review low-power feature roadmap.
Execute lab-based power measurements, correlate silicon data with modelling.
Document performance and power analysis, competitive analysis findings, and architectural recommendations for internal stakeholders.