AI GPU Cache Designer

Intel•Hillsboro, CA

1d•Onsite

About The Position

As a SoC Cache Design Engineer, you will play a pivotal role in developing cutting-edge Cache subsystem design for Intel's AI SoCs. You will drive the micro architecture, register transfer level (RTL) coding, subsystem integration, and simulation processes to deliver high-quality, fully verified Cache that meet power, performance, and area targets. Your work will directly contribute to Intel's groundbreaking AI hardware solutions, ensuring they meet the rigorous demands of modern applications. Intel's AI SoC organization is at the forefront of developing innovative products that power AI applications across diverse domains. From edge devices to data center accelerators, our team focuses on delivering high-performance, efficient, and scalable hardware solutions. As part of this group, you will collaborate with world-class engineers to advance Intel's leadership in AI hardware development and help shape the future of intelligent computing.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience.
Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration.
Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures.
Demonstrated ability to address design challenges, including clock domain crossings, power optimization, and timing closure.
Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization.

Nice To Haves

Strong knowledge of high-speed and low-power design techniques.
Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
Experience in SoC multicore CPU subsystem design and GPU cache development.
Collaborative mindset and leadership skills, with a passion for innovation and solving complex technical challenges.

Responsibilities

Evaluate architectural trade-offs to align design features with performance targets, power constraints, and system limitations.
Define and document microarchitecture specifications for complex SoC IP blocks, implement RTL in Verilog/SystemVerilog, and deliver synthesis- and timing-clean designs.
Collaborate closely with verification teams to ensure comprehensive validation and coverage of all design aspects.
Develop and maintain timing constraints for IP blocks, supporting physical design teams in synthesis, timing closure, and formal equivalence checks.
Lead silicon bring-up efforts, including post-silicon validation, debug, and performance analysis.
Mentor junior engineers and contribute to advancing best practices for design methodology and quality assurance.