AI Compiler Engineer

Ericsson • Austin, TX

5d • Onsite

About The Position

This is not a remote work opportunity. MLIR Architecture | Compiler Infrastructure | 5G/6G Silicon | Bare-Metal AI. Most AI compiler engineers optimize models for GPUs that already exist. You're going to optimize them for silicon that doesn't yet. As our Senior AI Compiler Engineer, you're not porting a framework, tweaking a runtime, or wrapping CUDA libraries. You're doing something far rarer and far harder — building a complete MLIR-based compiler stack from the ground up, purpose-built to run massive AI models like Llama 3 on bare-metal 5G/6G telecommunications silicon, where there's no OS to bail you out and every byte of memory is accounted for. The gap between a research model and hardware-optimized silicon execution is one of the most technically brutal problems in the industry right now. You'll be the engineer who closes it.

Requirements

• MLIR Mastery — You've built custom passes and dialect conversions, written TableGen definitions, and navigated the full complexity of the MLIR framework in a real production context
• Compiler Fundamentals — Deep, hands-on C++ and LLVM expertise: IR structure, pass pipelines, and code generation pipelines that actually ship
• Framework Integration — You've exported and lowered real models from JAX, PyTorch, or TensorFlow — you understand the gap between a research checkpoint and a deployable IR
• Dialect Expertise — You know StableHLO or XLA at the op-semantics level, not just the API surface

Nice To Haves

• Experience targeting Embedded DSP or VLIW architectures — instruction scheduling, register pressure, the works
• Advanced optimization depth: loop tiling, vectorization, quantization lowering, fixed-point arithmetic
• Hardware-level awareness of DMA engines, multi-level memory hierarchies, and complex number handling in MLIR — the stuff most compiler engineers never touch

Responsibilities

• Design and implement custom MLIR dialects from scratch — TableGen definitions, transformation passes, and the dialect conversion infrastructure that bridges the world of high-level AI graphs and the cold, hard reality of custom silicon.
• Take high-level computational graphs exported from JAX and StableHLO and lower them, step by step, into hardware-specific IR without losing a single bit of mathematical fidelity. Every op must legalize. Every semantic must survive the descent.
• Build static scheduling and tiling passes that choreograph data movement between HBM and on-chip local memory with surgical precision.
• Maintain a high-performance, modular, LLVM-based compiler codebase where correctness and determinism aren't aspirational — they're required.

Benefits

• Choice of three medical plan options
• Dental plan option
• 401(k) Plan with automatic 3% company contribution
• Company match $1 for $1 on the first 3% of eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
• Company-paid basic life insurance
• Company-paid basic accidental death and dismemberment coverage
• Company-paid short-term and long-term disability coverage
• Option to participate in Ericsson’s Stock Purchase Plan
• Minimum of 15 days of accrued vacation
• Up to 3 personal days per year
• 11 annual holidays
• 8 hours of volunteer time
• 80 hours of sick time annually
• Up to 16 weeks of paid maternity leave
• 6 weeks of parental or adoption leave at 100% of pay
• Financial wellness programs
• Educational assistance
• Matching gifts
• Recognition programs

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed