AI Architect, Agentic AI for Chip Design & EDA

Altera • San Jose, CA

1d • $209,500 - $295,000 • Onsite

About The Position

We are seeking a visionary and highly technical leader to drive the next generation of AI-powered semiconductor design solutions. This role will lead the development of Agentic AI, Generative AI, and machine learning technologies that transform the end-to-end silicon development lifecycle, from architecture and RTL development through physical design, manufacturing, and yield optimization.

The ideal candidate combines deep semiconductor expertise with advanced AI/ML experience and has a proven track record of building innovative software platforms, automation frameworks, and AI-driven design solutions. This individual will partner closely with design engineering, EDA, manufacturing, and data science teams to accelerate productivity, improve PPA (Power, Performance, and Area), reduce design cycle times, and advance autonomous chip design capabilities.

Requirements

• Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field.
• 12+ years of semiconductor industry experience with expertise spanning multiple phases of the silicon lifecycle.
• Deep understanding of digital IC design, RTL development, synthesis, physical implementation, timing closure, verification, and signoff methodologies.
• Strong expertise in AI/ML technologies, including Generative AI, LLMs, reinforcement learning, graph neural networks, and predictive modeling.
• Advanced programming skills in Python and one or more of C/C++, Java, or similar languages.
• Experience building enterprise software, AI platforms, analytics applications, or automation systems.
• Proven technical leadership experience leading large-scale engineering initiatives.
• Strong understanding of semiconductor manufacturing, yield analysis, DTCO, or design enablement.

Nice To Haves

• Experience developing Agentic AI systems for engineering or semiconductor applications.
• Hands-on expertise with leading EDA tools and workflows from Cadence, Synopsys, Siemens EDA, or equivalent platforms.
• Experience developing domain-specific LLMs, RAG architectures, AI copilots, or autonomous workflow solutions.
• Expertise with cloud computing, distributed systems, Spark, data engineering, and large-scale AI infrastructure.
• Knowledge of 3D-IC, advanced packaging, silicon photonics, advanced process technologies, or foundry operations.
• Track record of patents, publications, conference presentations, or industry-recognized technical contributions.
• Experience leading global, multidisciplinary engineering teams.

Responsibilities

• Lead the strategy, architecture, and development of AI-driven solutions for semiconductor design and optimization.
• Develop and deploy Agentic AI systems that automate complex engineering workflows across RTL, synthesis, physical design, signoff, DRC, power planning, validation, and 3D-IC design.
• Build intelligent multi-agent platforms capable of autonomous decision-making, design exploration, and flow optimization.
• Advance domain-specific Large Language Models (LLMs) and foundation models tailored for semiconductor workflows.
• Drive applications leveraging Retrieval Augmented Generation (RAG), AI copilots, code generation, and autonomous engineering agents.
• Lead AI initiatives that improve chip Power, Performance, Area (PPA), manufacturability, reliability, and silicon yield.
• Develop machine learning and reinforcement learning solutions for automated design space exploration and optimization.
• Apply Graph Neural Networks (GNNs), deep learning, and predictive analytics to accelerate semiconductor design convergence.
• Partner with product and engineering teams to integrate AI capabilities into commercial EDA platforms.
• Architect enterprise-scale AI and analytics platforms supporting EDA workloads and semiconductor design data.
• Develop scalable software systems utilizing Python, C/C++, databases, cloud infrastructure, big data technologies, and distributed computing frameworks.
• Create full-stack applications that analyze design data, identify bottlenecks, and provide actionable optimization recommendations.
• Build and maintain large-scale data pipelines, analytics frameworks, APIs, and AI application infrastructure.
• Drive Design Technology Co-Optimization (DTCO) initiatives linking design, process development, manufacturing, and yield learning.
• Develop AI/ML solutions for defect analysis, hotspot detection, manufacturability assessment, and yield prediction.
• Leverage silicon learning and manufacturing data to establish closed-loop optimization methodologies.
• Partner with foundry, silicon validation, and design enablement teams to improve technology development and production ramp efficiency.
• Serve as a thought leader in AI for semiconductor design and EDA.
• Lead cross-functional engineering teams and mentor senior engineers, researchers, and architects.
• Influence product roadmaps and represent the company at industry conferences, customer engagements, and technology forums.
• Drive innovation through patents, publications, and strategic partnerships.

Benefits

• The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree