Advanced Power Integrity & Power Delivery Architect

Rivian•Palo Alto, CA

12h•Onsite

About The Position

We are seeking a highly skilled and motivated Power Integrity & Power Architecture Engineer to lead the end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC power delivery architectures. In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture, silicon packaging, and system-level power integrity.

Requirements

Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Proven industry experience in Power Integrity (PI), Power Architecture for SoCs and advanced 2.5D/3D/MCM packaging.
Deep understanding of System-on-Chip (SoC) power distribution, package stack-ups, bump/ball maps, and silicon-package interactions.
Expertise in EM & Extraction tools such as Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS.
Expertise in Circuit & PDN Simulation tools such as HSPICE, Spectre, ADS, or SIMPLIS/SIMetrix.
Hands-on expertise with high-speed lab equipment (VNAs, oscilloscopes, active probes, impedance analyzers, load steppers) for physical power validation and PDN characterization.
Strong foundation in power architecture, electromagnetics, transmission line theory, s-parameters, and power distribution network (PDN) noise dynamics.

Nice To Haves

Proficiency in Python, Tcl, Perl, or Cadence SKILL for automating simulation and extraction pipelines.
Experience with Verilog-A, AMS, or SystemC for macro-level system power modeling.
Familiarity with high-speed interfaces (e.g., PCIe, DDR, UCIe, die-to-die interconnects) and mitigating power supply switching noise impacts on high-speed signals.

Responsibilities

Define and optimize overall SoC power architecture, establishing target impedance, transient droop specifications, and efficiency targets across the full path: SoC/Packaging/Board.
Define requirements and simulation flows for next-generation power supplier architectures, such as IVRs, integrated switching regulators. Co-optimize power delivery for high efficiency, low supply ripple, tight transient droop targets, and strict thermal limits across the SoC, package and system.
Perform co-design and co-optimization for silicon packaging, interposers, embedded passives to ensure robust power integrity.
Conduct pre- and post-layout power integrity (PI), signal integrity (SI), and IR/droop simulations using industry-standard 2.5D/3D field solvers and circuit simulators.
Lead post-silicon validation and silicon power integrity measurements (micro-probing, high-frequency VNAs, transient load steppers, real-time scope measurements for PDN noise) to correlate lab data with pre-silicon simulation models.
Collaborate with hardware and SoC bring-up teams to validate SoC platforms under real-world dynamic workloads, verifying transient performance, decoupling strategies, and power delivery margins.
Work alongside CAD and tool teams to automate power integrity analysis, extraction workflows, and simulation scripts (Python, Tcl, SKILL).