Advanced Packaging Design Verification & Physical Validation Engineer

Marvell Technology•Burlington, VT

50d•Onsite

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Marvell Advanced Packaging Design team is responsible for supporting customers with package solutions that meet challenging electrical requirements. High speed signaling and complex power delivery networks require new and custom solutions to meet constantly advancing application needs. Many of the new designs require multi-chip and multiple component configurations with high-speed IP requirements. In addition, our team is advancing Marvell's expertise in 3D packaging, Co-packaged optics and cutting-edge substrate materials. We work with the world's leading manufacturers to solve our client's most challenging designs and integrations with industry-leading packaging techniques. We are looking for an experienced engineer to join our Advanced Packaging Design team in Burlington, VT as a Package Design Verification Specialist. In this role, you will be the gatekeeper of design quality, responsible for running critical verification flows including DRC, LVS and DFM. A core focus of this position is driving process refinement and efficiency. You will champion a "shift-left" approach, integrating physical design validation earlier into the development cycle to catch errors sooner, accelerate time-to-market, and optimize overall design execution, while also executing and owning physical verification of package designs. We are looking for an engineer who wants to step up and own process improvement and execution on product. In this role, you will be running DRC, LVS, and DFM while actively executing physical design validation workflows to help our design team catch errors long before final tape-out.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, and 3+ years of experience in semiconductor design or manufacturing roles
Proven experience driving quality improvement, design or process validation.
Strong analytical mindset with a passion for finding structural gaps in engineering workflows.
Excellent communication skills to bridge the gap between R&D architects, layout designers, tool vendors, and external suppliers.
Ability to work in a fast-paced, highly collaborative R&D environment.
Strong scripting skills (TCL, Python, Perl, or Skill) to execute and automate verification tasks and data analysis.

Nice To Haves

Running and debugging DRC, LVS, and DFM on complex silicon or packaging layouts.
Experience with industry-standard physical verification tools (e.g., Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus).
Familiarity with advanced packaging technologies (e.g., 2.5D/3D IC, Chiplets, CoWoS, silicon interposers, or high-density fan-out architecture).

Responsibilities

Own and execute comprehensive PKG floor-planning Checks, DRC (Design Rule Checking), LVS (Layout Versus Schematic), and DFM (Design for Manufacturability) flows for complex, multi-die advanced packaging architectures.
Refine and optimize engineering workflows by implementing automated validation checkpoints early in the design cycle to minimize late-stage layout iterations.
Identify bottlenecks in the current verification pipeline and help develop automated scripts, custom methodologies, or enhanced design kits to boost layout efficiency.
Partner closely with Package Architects, Physical Layout Designers, and Supply Partners to resolve complex violation reports and interpret cutting-edge foundry design rules.
Author clear engineering documentation for newly established verification processes and train other members on these methodologies.