3rd Party Memory PHY Technical Lead

Advanced Micro Devices, Inc•Austin, TX

13d•Hybrid

About The Position

The candidate will join a highly visible and influential team of high-speed physical interface (PHY) and mixed signal IP experts tasked with integration and support of 3rd Party Memory/Serdes PHY and mixed signal IP across all AMD products. The team works across a large swath of AMD integration and post-silicon teams as well as with IP vendors and AMD customers.

Requirements

Self-motivated to work independently as well as collaboratively with technical people across a variety of AMD and vendor/partner teams.
Problem solver mindset.
B.S. or M.S. Electrical Engineering preferred
Strong experience designing high-speed mixed-signal IP, ideally with system-level architecture experience.
Breadth of knowledge across the full IP hardware development process (or strong interest in developing it) and experience with integration IP into an SOC
Design knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks, plus general mixed-signal IP, e.g. CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO, etc.
Experience with advanced FinFET semiconductor technologies at and below 7nm.
Basic understanding of RTL, logic design, and digital circuits
Strong analytical/problem solving skills, ability to learn quickly, and attention to detail.
Good teamwork and oral and written communications skills are critical.

Nice To Haves

Experience with one or more interface protocols like HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI etc. is preferred.
Python and/or Perl programming desirable.
Familiar with UNIX environment.
Laboratory experience, including hands-on use of equipment: BERT, oscilloscope, logic analyzer, etc. desirable.

Responsibilities

Serve as the AMD technical owner for selected third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs.
Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture --> integration --> post-silicon validation --> production.
Collaborate directly with third-party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs; working closely with the Technical Project Manager.
Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
Drive system-level architectural decisions by balancing performance, power, area, cost, and implementation constraints.
Interpret industry standards and customer requirements, translating them into silicon, package, PCB, and validation specifications.
Support package and PCB design teams with signal integrity and power integrity analysis, debug, and optimization; Partnering with SI/PI experts within AMD.
Evaluate new PHY and mixed-signal IP technologies for licensing and adoption.
Partner with post-silicon validation teams in directing first-silicon bring-up, debug, characterization, compliance testing, ATE production test support, and customer issue resolution.
Analyze post-silicon results and drive improvements to future PHY architectures, design methodologies, and IP development processes.
Provide technical guidance across the hardware development lifecycle, leveraging understanding of transistor-level design, system architecture, and SoC integration.