Workload / Performance Model Lead

SiFive•Austin, TX

17h

About The Position

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: The Role: SiFive, a leader in RISC-V CPU IPs, is looking for an experienced leader to lead benchmarking and performance infrastructure development. The candidate will be responsible for guiding the performance team to develop benchmarks for evaluating CPU / accelerator performance. The candidate will also be responsible for guiding the team to develop and deploy performance tools needed for architecture development / evaluation.

Requirements

MS or PhD in Computer Science / Computer Architecture
10+ years direct industry experience in performance simulation tools - from ISA to SoC / system simulators; from analytical to cycle-based models; from bare-metal environment to virtual machines.
5+ years involved in the engineering team to deliver HW or SW products.
Strong foundation in computer architecture of high performance out-of-order CPU designs. Awareness of known industry micro-architectures is a plus.
Strong foundation in workload characterization to identify HW/SW performance bottlenecks
Strong foundation in workload reduction techniques for efficient performance simulation and projection
Competency in software engineering best practices needed to maintain and refactor very large object oriented code bases.
Strong object-oriented programming (OOP) skills, including encapsulation, class coherency, inheritance and polymorphism
Strong Discrete Event Simulation (DES) competency, particularly with regard to DES modeling techniques and best practices
Ability to independently analyze performance bottlenecks in micro-architecture and software stack. Awareness of potential security holes is a plus.

Nice To Haves

Hands-on expertise with either HW development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or SW development (C/assembly, OS/RTOS, IDEs, Compiler/Debuggers).
FPGA debug, including the use of Integrated Logic Analyzer for waveform capture and debug
Familiar with git and branching/forking methodologies

Responsibilities

Identify, prepare (develop or port and setup), analyze performance for processor / accelerator development.
Analyze performance bottlenecks in micro-architecture and software stack.
Develop innovative methods to characterize workloads on simulators, emulators and/or hardware platforms.
Develop performance projection methodology for complex workloads
Develop and deploy efficient tools and infrastructure for performance evaluation