VLSI Timing Methodology Intern - Summer 2026
About The Position
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer Intern to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, informative analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence! We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
Requirements
- Pursuing BS or MS in Electrical or Computer Engineering.
- Understanding of CMOS circuit design in FinFET technology and mathematics/physics fundamentals of electrical design.
- Experience with 3DIC design flows and related technologies.
- Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS), CDC, signal/power integrity, etc.
- Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.
- Experience with coding - TCL, Python - and familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.
Responsibilities
- Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
- Work on various aspects of STA, constraints, timing and power optimization.
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What This Job Offers
Career Level
Intern
Industry
Computer and Electronic Product Manufacturing
Number of Employees
5,001-10,000 employees
