VLSI Design Automation Intern, Applied AI - Summer 2026

NVIDIASanta Clara, CA
1d$20 - $71

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. We are looking for a VLSI CAD Timing Intern focused on Applied AI to lead end-to-end solution development — spanning data generation, model training, orchestration, and agentic automation — for timing and constraint analysis workflows. You will be part of a cross-disciplinary team building intelligent systems that learn from sign-off data, reason across flows, and assist engineers in achieving faster and more predictable closure.

Requirements

  • Currently pursuing a Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Exposure to Applied Agentic AI.
  • Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
  • Familiarity with the basics of static timing analysis, constraints, or digital design flows.
  • Knowledge in scripting or programming (Python preferred).
  • Comfort working with data, reports, and technical problem-solving in complex systems.

Nice To Haves

  • Academic projects, research, or internships related to VLSI, physical design, STA, or EDA tools.
  • Exposure to machine learning, data analysis, or AI concepts applied to engineering problems.
  • Exposure to TCL.
  • Experience automating workflows, analyzing large datasets, or contributing to technical tools or open-source projects.

Responsibilities

  • Learn and support static timing analysis (STA) flows using industry tools like PrimeTime and Tempus for advanced ASIC designs.
  • Help develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
  • Assist with analyzing timing reports, constraints, and design data across corners and modes to improve closure predictability.
  • Collaborate with CAD, physical design, and methodology engineers on timing sign-off strategies and best practices.
  • Contribute to early AI- or analytics-assisted approaches for timing analysis, constraint checking, or flow optimization.
  • Explore how physical effects (e.g., IR drop, crosstalk, aging, thermal impact) influence timing and design decisions.

Benefits

  • You will also be eligible for Intern benefits.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service