Test Engineer ATE - Contract

D-Matrix • Santa Clara, CA

54d • Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. Job Description We are looking for ATE Test Engineer - Contract with proven experience in developing and supporting complex silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of CPU, communication/interface protocols such as PCI-Express (Gen-4/5/6), High Speed D2D, LPDDR(4/5/6), etc. The candidate will also need work with OSAT to identify, drive test cost reduction, improve both CP and FT yield, Identify FT high yield fallout bins and enhance CP program to minimize such high FT yield fallout bins.

Requirements

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred.
• 8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.
• Hands-on experience with high-speed SoC test program/hardware development on Advantest 93k test platform.
• Collaboration with design DFT team to define test strategy, create and own test plan.
• Familiar with high-speed and high power load board design techniques
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests.
• Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block
• Proficiency in modern programming languages such as C/C++, Python.

Nice To Haves

• Fluent in data processing using high level programming languages.
• Experience in running internal loopback at wafer sort as well as at FT.
• Familiarity database setup using JMP as YMS (Yield Management Tool).

Responsibilities

• Develop and oversee SoC test strategy
• Interact with manufacturing partners
• Define and implement ATE programs
• Own the product from design, initial samples all the way through high volume production ramp
• Work with OSAT to identify, drive test cost reduction, improve both CP and FT yield
• Identify FT high yield fallout bins and enhance CP program to minimize such high FT yield fallout bins

What This Job Offers

• Career Level: Mid Level
• Industry: Publishing Industries
• Number of Employees: 101-250 employees