Technical Staff Engineer - Verification

Microchip Technology Inc.•Chandler, AZ

20d•$91,000 - $232,000

About The Position

The FPGA Business Unit of Microchip Technology Inc is seeking an experienced and innovative verification engineer for our team in Chandler, Arizona to work on the verification of our next generation, highly secure, low-power FPGA device products.

Requirements

12+ years in functional verification of complex SoC designs
Expertise in System Verilog, UVM, formal verification methodologies
Proven experience in methodology development and tool automation.
Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
Good understanding of SoC architectures – ARM/RISC-V
Expertise in at least two of the following domains/peripherals CPU subsystems PCIe Gen3/Gen4/Gen5 DDR4/DDR5, LPDDR4X MIPI DSI/CSI Ethernet MAC USB Security and cryptography IPs.
Exposure to emulation, hardware prototyping and post-silicon debug
Experience with FPGA-based acceleration platforms and simulation/emulation flows.
Software & Scripting: Python, TCL/TK, and C/C++ for automation and validation.
Tools: Familiarity with Siemens/Cadence/Synopsys verification suites Revision control systems (Git, Perforce, svn).
Excellent debug skills
Experience working with global cross functional teams
Excellent communication and collaboration skills
BS or MS in Electrical/Electronic Engineering with 12+ years of experience

Nice To Haves

Strong understanding of FPGA architecture
Experience with coverage-driven verification using ML-based optimizations.
Experience in emulation, hardware prototyping and post-silicon debug,
Knowledge and exposure to complete SOC RTL to GDS to silicon release flow.

Responsibilities

Verification of complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.
Develop and maintain highly reusable UVM based test benches and verification environments.
Involve in RTL, power aware and gate level verification.
Contribute to quality and productivity be using AI/ML-enabled verification methodologies
Collaborate with emulation and hardware prototyping teams to define a unified verification methodology.
Collaborate with architecture and design teams to ensure seamless execution and first-silicon success.
Mentor junior team members.