Staff Design Verification Engineer

Analog Devices • Somerset, NJ

2h • $131,285 - $190,108

About The Position

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability. Working with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.

Requirements

• SystemVerilog and UVM Expertise : Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs
• Test Planning and Strategy : Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure
• Debugging Mastery : Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction
• EDA Tool Proficiency : Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques
• Scripting and Automation : Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks
• MS in Electrical Engineering, Computer Engineering, or related field
• 7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification

Nice To Haves

• Mixed-Signal Verification : Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches

Responsibilities

• Plan, develop, document, and execute comprehensive verification strategies across simulation and emulation for block, subsystem, and full-chip designs.
• Build, enhance, and maintain SystemVerilog UVM-based verification environments, infrastructure, and flows, including Matlab/C/SystemC model validation.
• Develop and debug constrained-random and directed test suites across chip hierarchies aligned with verification plans.
• Define and implement functional coverage, assertions, and metrics to track verification progress and drive closure.
• Lead verification reviews, analyze coverage results, and drive actions to close coverage gaps.
• Evaluate, unify, and continuously improve verification methodologies to increase productivity and efficiency.
• Collaborate with global teams to integrate internal and third-party IP/VIP into the verification environment.
• Partner with cross-functional teams (design, architecture, software, implementation) to ensure robust design quality and on-time delivery.

Benefits

• At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.
• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level