Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Amazon • Austin, TX

2d

About The Position

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a Sr. Signal & Power Integrity Engineer to join our hardware team and drive the SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs. In this role, you will own the package-level signal and power integrity strategy — from early architecture trade-offs through design closure, measurement and validation. You'll work at the intersection of IC, package, and board, ensuring our advanced packaging technologies meet dynamic performance, power delivery, and manufacturing targets.

Requirements

• Bachelor's degree in Electrical Engineering or a related field
• 10+ years of experience in signal integrity, power integrity, and package design
• Deep expertise in package SI/PI analysis: S-parameter extraction, PDN impedance analysis, IR drop, crosstalk, and return loss
• Hands-on experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent
• Strong understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects
• Experience analyzing and modeling decoupling technologies including on-die MOM/MOS capacitors, deep trench capacitors (DTCs), and IPD capacitors within the package PDN
• Proficiency in stack-up design and impedance control for multi-layer organic substrates and silicon interposers
• Hands-on experience correlating package SI/PI simulations with lab measurements (TDR, VNA, oscilloscope)

Nice To Haves

• Master's in Electrical Engineering or related field
• 7+ years of experience, in signal integrity, power integrity, and package design
• Experience with UCIe or other die-to-die interconnect standards in advanced packaging contexts
• Familiarity with package-level thermal-aware PI analysis and electromigration considerations
• Experience with EMC/EMI analysis and mitigation at the package level
• Experience with high-speed serial protocols (PCIe Gen6/7, UCIe, or custom SerDes) at the package level
• Knowledge of package co-design methodologies (chip-package-board co-simulation)
• Experience with high-density fan-out or silicon bridge packaging (e.g., EMIB, CoWoS, or similar)
• Experience with PDN target impedance methodology and frequency-domain decoupling optimization across die, package, and board domains

Responsibilities

• Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
• Design and optimize package stack-ups: dielectric material selection, impedance control, layer assignment, and RDL routing for high-speed and power delivery performance.
• Perform high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces through the package.
• Analyze and optimize the package PDN end-to-end: decoupling strategy, plane resonance, IR drop, and AC impedance from die bumps through substrate to board.
• Characterize and model on-die capacitance, deep trench capacitors (DTCs), and integrated passive device (IPD) capacitors; evaluate their effectiveness within the full-stack PDN impedance profile.
• Interface with SoC die-level PDN teams to align power grid requirements, current profiles, and decoupling budgets across the chip-package boundary.
• Perform 3D/2.5D EMIR analysis using tools such as Ansys RedHawk-SC 3DIC, Cadence Voltus, or equivalent to validate IR drop and electromigration across multi-die stacked packages.
• Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for both signal and power paths.
• Apply equalization techniques (DFE, CTLE, FFE) and evaluate package-level channel margins for PCIe, UCIe, and custom die-to-die links.
• Perform clock distribution and jitter analysis at the package level, accounting for coupling, skew, and return path discontinuities.
• Collaborate with ASIC design, board design, and packaging/assembly teams to co-optimize package architecture for electrical performance and manufacturing yield.
• Identify and mitigate package manufacturing risks — warpage, via reliability, impedance variation, and material tolerance impacts on SI/PI.
• Develop and maintain package SI/PI modeling flows, automation scripts, and design guidelines.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level