Sr. Analog Design Engineer

OMNIVISION • Santa Clara, CA

1d

About The Position

The Sr. Analog Design Engineer will be responsible for the design and development of image sensor technologies, including transistor-level design of analog and mixed-signal circuits for CMOS Image Sensors using Cadence Virtuoso. This role involves working on analog and mixed-signal circuit layout design, collaborating with layout engineers for whole chip integration and verification, and performing extensive simulations and design verification using various industry-standard CAD tools. The engineer will also be involved in extracting parasitic parameters, processing simulation data, developing test bench scripts, and collaborating with digital, verification, process, test, and application engineers to optimize fabricated image sensors. A key aspect of the role is to propose innovative solutions and engage in new circuit R&D to stay ahead of current technology.

Requirements

• Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of experience in analog circuit, digital circuits and semiconductor device physics.
• Tape-out experiences of CMOS analog and mixed-signal integrated circuits (ICs).
• Industry-standard CAD tools for analog design, such as Cadence Virtuoso for schematic design, Cadence Spectre, LTspic for simulation, and DRC, LVS Calibre for layout.
• Digital hardware design using HDLs and RTL design, with hands-on experience in FPGA development using Xilinx Vivado.
• Arduino and Bluetooth Low Energy (BLE) microcontroller programming.
• Printed circuit boards (PCB) design and layout, using tools such as Autodesk Eagle.
• Scripting and numerical computing with Python and MATLAB for simulation, automation, and data analysis.
• Chip test, verification, debug and measurements using lab equipment such as oscilloscopes, function generators, and data acquisition (DAQ) systems.

Responsibilities

• Conduct design and development of image sensor technologies in advanced sub-micron node, including finfet.
• Work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso.
• Work on analog and mixed signal circuits layout design by Cadence Layout tool, such as column_array.
• Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
• Perform sub-blocks and whole image sensor readout circuit simulation (DCG function, noise, PSRR, H-banding, etc.) by simulators such as Cadence Spectre, Analog FastSPICE (AFS), Empyrean ALPS and NanoSpice.
• Perform design verification such as DRC, LVS, antenna rule, and PERC check by using Siemens Caliber tools.
• Extract post-layout parasitic parameters by Calibre PEX.
• Process simulation data and develop script for test bench.
• Collaborate with Digital Engineer to define and design the analog to digital interface and timing generation.
• Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors.
• Propose innovative and creative solutions along with new circuit R&D and be ahead of current technology.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 501-1,000 employees