SoC Power Architect (Principal Engineer)

Samsung•Austin, TX

21h•$221,700 - $364,800

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a SoC Power Architect, you will lead and contribute hands-on to the design and validation of power models for Samsung’s next-generation semiconductor designs. In this high-impact, highly visible role, you will play a crucial role in accurately predicting power consumption, optimizing energy efficiency, and ensuring the success of cutting-edge integrated circuits. In collaboration with global cross-functional teams, your deep expertise in power modeling tools and methodologies will help deliver solutions that power next-generation consumer mobiles and adjacent markets. You lead the development of accurate power models across multiple levels of design abstraction, from RTL to gate level, leveraging industry-standard tools and methodologies. You engage closely with coherent interconnect, memory controller, and last level cache (LLC) design specifications—evaluating implementation choices and performance implications. You validate and refine models through simulation and real-world power measurements, ensuring end-to-end correlation from model to post-silicon, and analyze results to uncover power-saving opportunities and guide design teams with data-driven recommendations. You lead collaboration with global teams, including architects, micro-architects, and physical design, to define power-saving microarchitectural features, align on requirements, and integrate models seamlessly into the design flow. You inspire engineering excellence by mentoring engineers, fostering ownership, promoting open communication, and continuously learning and experimenting with emerging power modeling techniques, standards, and tools. Our Team The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments. Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation.

Requirements

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a Ph.D.
Deep experience in power modeling and analysis for complex semiconductor designs, with silicon power measurement expertise.
Deep understanding of digital design concepts, dynamic and leakage power tradeoff.
Strong understanding of mobile chip architecture and design concepts, including mobile scenarios, DVFS sequences, and PMIC operation.
Strong proficiency in programming languages like Python, C++ for power modeling and analysis
Solid understanding of memory subsystems, including interconnect, last-level cache, coherency, and memory controllers (DDR, LPDDR, or HBM), along with DRAM power understanding.
Effective attention to details, with the ability to multitask in a fast-paced, dynamic environment.
Excellent analytical and problem-solving skills, with the ability to influence decisions using data-driven approach.
Excellent communication and collaboration skills, with the ability to navigate ambiguity in a global team environment.

Responsibilities

Lead the development of accurate power models across multiple levels of design abstraction, from RTL to gate level, leveraging industry-standard tools and methodologies.
Engage closely with coherent interconnect, memory controller, and last level cache (LLC) design specifications—evaluating implementation choices and performance implications.
Validate and refine models through simulation and real-world power measurements, ensuring end-to-end correlation from model to post-silicon, and analyze results to uncover power-saving opportunities and guide design teams with data-driven recommendations.
Lead collaboration with global teams, including architects, micro-architects, and physical design, to define power-saving microarchitectural features, align on requirements, and integrate models seamlessly into the design flow.
Inspire engineering excellence by mentoring engineers, fostering ownership, promoting open communication, and continuously learning and experimenting with emerging power modeling techniques, standards, and tools.